The present invention is generally drawn to reducing the time (or CPU cycles) needed to write to a register.
In today's market, many of the system on chips (SOC) feature at least one embedded microprocessor. A significant task handled by the microprocessor is the programming of the various registers in the SOC. Most of often, the programming is done through a read-modify-write mechanism by the firmware. This mechanism is inefficient in terms of the CPU cycles needed for each register update. A conventional read-modify-write mechanism will now be described with reference to FIG. 1.
FIG. 1 illustrates a conventional Read-Modify-Write mechanism 100.
As shown, Read-Modify-Write mechanism 100 includes an address decoding logic component 102, a bit register 104, a bit register 106, and a bit register 108. Bit register 104 includes a MUX 110 and a Flip-Flop 112, bit register 106 includes a MUX 114 and Flip-Flop 116, and bit register 108 includes a MUX 118 and a Flip-Flop 120.
Address decoding logic component 102 is arranged to receive an address signal by way of line 101. Address decoding logic component 102 is additionally arranged to output an enable signal to each of the bit registers 104, 106, and 108 by way of line a write line 122.
Bit registers 104, 106, and 108 are arranged to receive a clock signal by way of line 148. Bit registers 104, 106, and 108 are additionally arranged to output one of the stored bits of data by way of a read line 124, 126, and 128 respectively.
MUX 110 is arranged to receive data at an input 136 from a write line 156 and to receive at an input 130 from read line 126. MUX 114 is arranged to receive data at an input 138 from a write line 158 and to receive at an input 132 from read line 126. MUX 118 is arranged to receive data at an input 140 from a write line 160 and to receive data at an input 134 from read line 128.
Finally, Flip-Flop 112, 116, and 120 are arranged to output data via read lines 124, 126, and 128, respectively and to receive data at a clock input 162, 164, and 166 from a clock signal line 148. Each flip-flop also includes a D-input 142, 144, and 146.
The operation of the read-modify-write mechanism 100 begins with a read command. When the mechanism is prompted to do a read, a signal is sent on read lines 124, 126, and 128 into bit registers 104, 106, and 108, respectively. Once the read signal is sent, the data currently contained in bit registers 104, 106, and 108 are forwarded from the output of flip-flops 112, 116, and 120 via read line 124, 126, and 128 to their corresponding MUX. At this point, each MUX 112, 116, and 120 has read-in the data and stores it at their corresponding inputs 130, 132, and 134. This completes the read step.
Next, read-modify-write mechanism 100 starts to modify what is in the registers. In this example, read-modify-write mechanism 100 discloses a set of three 1-bit registers associated with one address, that of address decoding logic component 102. It should be noted that there may be many sets of bit registers, each with an associated address decoding logic component. As such, for purposes of explanation, only the set of registers associated with address decoding logic component 102 are shown.
An address signal is sent via line 101 to address decoding logic component 102. Upon receipt of the address signal, address decoding logic component 102 outputs a value of “1” onto bus line 122. This value passes to each MUX (104, 116, 120), which enables the MUX to write-in the value via write lines 156, 158, and 160 to first inputs 136, 138, and 140, respectively, and then latch the new data to corresponding flip-flops 112, 116 and 120, respectively. As such, the data in each of flip-flops 112, 116 and 120 has now been modified. This completes the modification step.
After the modification step, the last step is to write-out the data from the output of flip-flops 112, 116, 120 via the read lines 124, 126, and 128 respectively.
The problem with the system shown in FIG. 1 is that there is an extra cycle required to first read in the data. This mechanism generally involves reading the entire content of each register, modifying all the bits, and then writing the entire content back to the register. This mechanism consumes a major portion of time.
What is needed is a system and method that does not require a read step, so the amount of time programming various registers can be reduced.